Memory mapper hardware notes by Charles MacDonald WWW: http://cgfm2.emuviews.com Unpublished work Copyright 2006 Charles MacDonald Table of Contents 1.) MB831001 2.) MB832011 3.) 315-5208 4.) 315-5235 5.) Credits and Acknowledgements 6.) Disclaimer ---------------------------------------------------------------------------- 1.) MB831001 ---------------------------------------------------------------------------- Overview The MB831001 is a mask ROM manufactured by Fujitsu with an integrated mapper. It comes in a 28-pin plastic DIP and has an access speed of 250ns. Features - ROM capacity of 128K - ROM banking in $8000-$BFFF Pin assignments +----v----+ Z80 /WR |01 28| +5V Z80 A12 |02 27| Z80 A14 Z80 A7 |03 26| Z80 A13 Z80 A6 |04 25| Z80 A8 Z80 A5 |05 24| Z80 A9 Z80 A4 |06 23| Z80 A11 Z80 A3 |07 22| /EXM2 Z80 A2 |08 21| Z80 A10 Z80 A1 |09 20| /SLOT-CE Z80 A0 |10 19| Z80 D7 Z80 D0 |11 18| Z80 D6 Z80 D1 |12 17| Z80 D5 Z80 D2 |13 16| Z80 D4 GND |14 15| Z80 D3 +---------+ * /EXM2 is A15 & /MREQ, so it functions as A15. Register functions $FFFF - Bank select for $8000-$BFFF D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 There is an alternate version of this chip with no Fujitsu marking and a different appearance (deeper pin 1 indicator notch, leads protrude further from the body). It has a date code stamped in the middle, and underneath that a string in the format of: "SEGA W" It functions identically to the MB831001. ---------------------------------------------------------------------------- 2.) MB832011 ---------------------------------------------------------------------------- Overview The MB832011 is a mask ROM manufactured by Fujitsu with an integrated mapper. It comes in a 32-pin plastic DIP and has an access speed of 250ns. Features - ROM capacity of 256K - ROM banking in $4000-$7FFF - ROM banking in $8000-$BFFF - SRAM support in $8000-$BFFF - SRAM support in $C000-$FFFF Pin assignments +---------+ GND |01 32| +5V SRAM A14 |02 31| SRAM /CS /WR |03 30| +5V A12 |04 29| Z80 A14 A7 |05 28| Z80 A13 A6 |06 27| Z80 A8 A5 |07 26| Z80 A9 A4 |08 25| Z80 A11 A3 |09 24| /EXM2 A2 |10 23| Z80 A10 A1 |11 22| /SLOT-CE A0 |12 21| Z80 D7 D0 |13 20| Z80 D6 D1 |14 19| Z80 D5 D2 |15 18| Z80 D4 GND |16 17| Z80 D3 +---------+ * /EXM2 is A15 & /MREQ, so it functions as A15. Any combination of pins 1,16,30,32 can be used to supply voltage to the chip. Pin 1 is always tied to ground and pin 30 is sometimes left unconnected; it allows a 32-pin socket to accomodate the 28-pin MB831001 as well as the MB832011. Typical SRAM configuration with this chip: /WE = Z80 /WR /OE = Z80 /RD /CS = SRAM /CS A14 = SRAM A14 Register functions $FFFC - Control register D4 : 1= SRAM mapped to $C000-$FFFF (*1) D3 : 1= SRAM mapped to $8000-$BFFF, 0= ROM mapped to $8000-$BFFF D2 : SRAM A14 state when $8000-$BFFF is accessed (1= high, 0= low) $FFFE - Bank select for $4000-$7FFF D3 : Bank address, bit 17 D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 $FFFF - Bank select for $8000-$BFFF D3 : Bank address, bit 17 D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 There is an alternate version of this chip with no Fujitsu marking and a different appearance (deeper pin 1 indicator notch, leads protrude further from the body). It has a date code stamped in the middle, and underneath that a string in the format of: "SEGA W" It functions identically to the MB832011. ---------------------------------------------------------------------------- 3.) 315-5208 ---------------------------------------------------------------------------- Overview The 315-5208 is a memory mapper manufactured by Sega. It comes in a 28-pin plastic DIP. Features - ROM capacity of 128K - ROM banking in $8000-$BFFF Pin assignments +----v----+ Z80 A5 |01 i i 28| Z80 A6 Z80 A4 |02 i i 27| Z80 A7 Z80 A3 |03 i i 26| Z80 A12 Z80 A2 |04 i i 25| Z80 /WR Z80 A1 |05 i s 24| GND Z80 A0 |06 i i 23| Z80 A14 GND |07 s o 22| BA14 Z80 A11 |08 i s 21| +5V Z80 A10 |09 i o 20| BA15 /EXM2 |10 i i 19| Z80 D0 /SLOT-CE |11 i i 18| Z80 D1 Z80 A13 |12 i i 17| Z80 D2 Z80 A8 |13 i o 16| BA16 Z80 A9 |14 i o 15| /ROM_CS +---------+ Typical ROM configuration with this chip: ROM /OE = Ground ROM /CS = /ROM_CS Register functions $FFFF - Bank select for $8000-$BFFF D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 ---------------------------------------------------------------------------- 4.) 315-5235 ---------------------------------------------------------------------------- Overview The 315-5235 is a memory mapper manufactured by Sega. It comes in a 42-pin plastic DIP. Features - ROM capacity of 512K - ROM banking in $0400-$3FFF - ROM banking in $4000-$7FFF - ROM banking in $8000-$BFFF - SRAM support in $8000-$BFFF - SRAM support in $C000-$FFFF - ROM bank shifting Pin assignments +----v----+ Z80 A7 |01 i i 42| Z80 A8 Z80 A6 |02 i i 41| Z80 A9 Z80 A5 |03 i i 40| Z80 A10 Z80 A4 |04 i i 39| Z80 A11 Z80 A3 |05 i i 38| Z80 A12 Z80 A2 |06 i i 37| Z80 A13 Z80 A1 |07 i i 36| Z80 A14 Z80 A0 |08 i i 35| Z80 A15 BA14 |09 o i 34| Z80 /RD BA15 |10 o i 33| /SLOT-CE GND |11 s s 32| +5V BA16 |12 o i 31| Z80 /WR BA17 |13 o o 30| SRAM /CS BA18 |14 o o 29| /GWR /ROM0 |15 o ? 28| ? (*1) /ROM1 |16 o ? 27| GND (*2) /ROM2 |17 o i 26| /RESET Z80 D0 |18 i i 25| MODE Z80 D1 |19 i o 24| /ERAM Z80 D2 |20 i i 23| Z80 D7 Z80 D3 |21 i i 22| Z80 D4 +---------+ 1.) Always high. Maybe an input, normally left unconnected. 2.) Likely another ground input, doesn't seem to function as a mode select. Pin functions /ROM0 = Asserted for reads from ROM banks: $00-$07 (1M mode) $00-$1F (4M mode) /ROM1 = Asserted for reads from ROM banks: $08-$0F (1M mode) $00-$0F (4M mode) /ROM2 = Asserted for reads from ROM banks: $10-$1F (1M mode) $10-$1F (4M mode) /ERAM = Asserted for work RAM access when bit 4 of $FFFC is reset. SRAM /CS = Asserted for SRAM access when mapped to $8000-$BFFF or $C000-$FFFF /GWR = Follows Z80 /WR, disabled when bit 7 of $FFFC is set. BA18-14 = Banked ROM address bits 18-14 MODE = ROM size mode, tie to +5V for 128K (1M) or ground for 512K (4M). The /ROMx signals are valid for accesses within $0000-$BFFF, or $0000-$7FFF when SRAM is enabled in $8000-$BFFF. SRAM access The bank number specified in $FFFF is still valid when SRAM is enabled within $8000-$BFFF, it will not be reset or otherwise modified. During access to $8000-$BFFF with SRAM enabled, BA18-BA15 output the bank number bits just like a regular ROM access. The exception is BA14 which is set to the value specified in $FFFC bit 2 to support SRAM banking. SRAM cannot be banked within $C000-$FFFF, BA14 is forced high. If 32K of SRAM was available, this would allow for a linear mapping of it from $8000-$FFFF if $FFFC had bits 4,3 set. During SRAM access the /ROMx strobes are not active, so the state of BA18-BA15 at that time is irrelevant. Mappper overview Depending on the ROM size mode selected, the following configurations can be used: 128K (1M) 512K (4M) /ROM0 128K or smaller 512K or smaller /ROM1 128K or smaller 256K or smaller /ROM2 256K or smaller 256K or smaller The total capacity for either mode is 512K, split across different ROM sizes. The /ROMx signals are output enable strobes, so ROMs should have their /CS inputs tied to ground and /OE to /ROMx. /ERAM seems to be specific for the Japanese SMS or Mark-III hardware, which may (like the SC-3000H) have a dedicated work RAM disable pin on the cartridge connector. /ERAM would facilitate disabling it automatically when cartridge SRAM was mapped to $C000-$FFFF. For a export (US/European) console, work RAM has to be manually disabled through bit 4 of I/O port $3E. /GWR also isn't used anywhere, though the official system documentation mentions it needs to be cleared for commercial (ROM-based) software and set for development. Presumably the development board hardware uses RAMs connected to /GWR for uploading program code. When /RESET is asserted, the registers are initialized as follows: $FFFC = $00 $FFFD = $00 $FFFE = $01 $FFFF = $02 Signal timing /ROM2-0 = Same as Z80 /RD pulse width /ERAM = Same as Z80 /WR or Z80 /RD pulse width /GWR = Same as Z80 /WR pulse width SRAM /CS = Same as /MREQ pulse width BA18-BA14 = Output change is triggered on Z80 A15-14 edge transition Register functions $FFFC - Control register D7 : 1= /GWR disabled (write protect), 0= /GWR enabled (write enable) D4 : 1= SRAM mapped to $C000-$FFFF (*1) D3 : 1= SRAM mapped to $8000-$BFFF, 0= ROM mapped to $8000-$BFFF D2 : SRAM banking; BA14 state when $8000-$BFFF is accessed (1= high, 0= low) D1 : Bank shift, bit 1 D0 : Bank shift, bit 0 The bank shift adds a constant to the bank number, wrapping at $1F to form a new bank number. D1 D0 0 0 : Add $00 (banks $00-$1F map to $00-$07,$08-$0F,$10-$17,$18-$1F) 0 1 : Add $18 (banks $00-$1F map to $18-$1F,$00-$07,$08-$0F,$10-$17) 1 0 : Add $10 (banks $00-$1F map to $10-$17,$18-$1F,$00-$07,$08-$0F) 1 1 : Add $08 (banks $00-$1F map to $08-$0F,$10-$17,$18-$1F,$00-$07) When the bank shift is set, none of the existing bank values in $FFFD-$FFFF are updated - the old values written are still latched. As soon as *any* bank select register is written to, then *all* registers are shifted. So generally speaking you cannot shift banks individually (it's all or none) and at least one register must be rewritten for the new bank shift value to take effect. The first 1K of ROM is always mapped to $0000-$03FF regardless of the bank number in $FFFD or the bank shift value. $FFFD - Bank select for $0400-$3FFF D7 : Unused D4 : Bank address, bit 18 D3 : Bank address, bit 17 D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 $FFFE - Bank select for $4000-$7FFF D7 : Unused D4 : Bank address, bit 18 D3 : Bank address, bit 17 D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 $FFFF - Bank select for $8000-$BFFF D7 : Unused D4 : Bank address, bit 18 D3 : Bank address, bit 17 D2 : Bank address, bit 16 D1 : Bank address, bit 15 D0 : Bank address, bit 14 ---------------------------------------------------------------------------- 5.) Credits and Acknowledgements ---------------------------------------------------------------------------- * shmike for his investigation of the 315-5235 mode switch function. * S8-Dev Team for the "Sega 315-5208, 315-5235, and 315-5365 Master System Memory Paging Chips" document. * Maxim for the connector pinouts and mapper chip information on the S8-Dev wiki. ---------------------------------------------------------------------------- 6.) Disclaimer ---------------------------------------------------------------------------- If you use any information from this document, please credit me (Charles MacDonald) and optionally provide a link to my webpage (http://cgfm2.emuviews.com/) so interested parties can access it. The credit text should be present in the accompanying documentation of whatever project which used the information, or even in the program itself (e.g. an about box) Regarding distribution, you cannot put this document on another website, nor link directly to it. Unpublished work Copyright 2006 Charles MacDonald